CD4063BMS is a 4-bit magnitude comparator designed for usein computer and logic applications that require the comparison oftwo 4-bit words. This logic circuit determines whether one 4-bitword (Binary or BCD) is “less than”, “equal to”, or “greater than” asecond 4-bit word.The CD4063BMS has eight comparing inputs (A3, B3, throughA0, B0), three outputs (A < B, A = B, A > B) and three cascadinginputs (A < B, A = B, A > B) that permit systems designers toexpand the comparator function to 8, 12, 16 . . . 4N bits. When asingle CD4063BMS is used, the cascading inputs are connectedas follows: (A < B) = low, (A = B) = high, (A > B) = low.For words longer than 4 bits, CD4063BMS devices may be cascadedby connecting the outputs of the less significant comparatorto the corresponding cascading inputs of the more significantcomparator. Cascading inputs (A < B, A = B, and A > B) on theleast significant comparator are connected to a low, a high, and alow level, respectively.

The CD4063BMS is supplied in these 16 lead outline packages:

Braze Seal DIP         H4T
Frit Seal DIP            H1E
Ceramic Flatpack     H6W


• High Voltage Type (20V Rating)

• Expansion to 8, 12, 16 . . . 4N Bits by Cascading Units

• Medium Speed Operation

- Compares Two 4-Bit Words in 250ns (Typ.) at 10V

• 100% Tested for Quiescent Current at 20V

• Standardized Symmetrical Output Characteristics

• 5V, 10V and 15V Parametric Ratings

• Maximum Input Current of 1ìA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC

• Noise Margin (Full Package Temperature Range)

- 1V at VDD = 5V

- 2V at VDD = 10V

- 2.5V at VDD = 15V

• Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard  Specifications for Description of ‘B’ Series CMOS Devices”



• Servo Motor Controls

• Process Controllers

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